1. Field of the Invention
The present invention generally relates to the field of semiconductor process controls and, more particularly, to methods for simulating device structures in integrated process studies.
2. Description of the Prior Art
Integrated process studies which simulate the steps used in manufacturing semiconductor devices use data structures to represent physical device structures. These studies typically consist of one to fifteen device layouts used to pattern films which are formed by one hundred to several hundred process steps. The process steps include depositions, wet etching, reactive ion etching (RIE), oxidations, chemical-mechanical polishing, implantations, and masking. It is desirable to obtain the simulation results in less than a few minutes so that many variations of layouts, film thickness, and overetches can be included as the semiconductor process is initially studied.
In the prior art, rectangular grids and triangular grids have been used in structure simulations. State of the art tools use a string algorithm for two dimensional simulations. Solids bounded by polygons have been used in three dimensional simulations. In the string algorithm, the boundaries between materials are represented by a sequence of vertices connected by straight lines at arbitrary slopes. These data structures have no natural extension for statistical simulations. Consequently, it is an exceedingly complex matter in the prior art to take into account variation in film thickness and etching and deposition rates within process control limitations.
There are two complications which arise during the simulations which are related to the data structure. The first is overetching, and the second is overfilling.
Overetching may occur during any film-removal process step, such as wet etching, reactive ion etching, oxidation, and chemical-mechanical polishing. When an initial film is completely removed in any region, underlying films are then exposed for the remainder of that process step. These underlying films usually would have a different removal rate from the initial film. The complication is in discovering which underlying films have been exposed and how much time is left in the removal step for each region where an overetch occurred.
Over filling may occur during any film-growth process step. These steps include oxidation and deposition, where growth in film thickness is in a direction normal to exposed surfaces. Thus a vertical surface will grow horizontally, forming a "sidewall". When two facing vertical surfaces grow in this fashion they may meet, thereby eliminating the vertical surfaces or "overfilling" the region between the two facing surfaces, that is, the simulation will generate and unphysical overlapping that does not occur in the real process. The occurrence of overfilling must be detected and the device structure representation modified appropriately in these regions.
The device structures which evolve during the simulations need to be represented compactly by the data structure for two reasons. First, it is desirable to be able to do these simulations on a personal computer (PC) to reduce their cost. This is important for memory limitations on a personal computer. However, the more important consideration is for speed of simulations, especially for statistical simulations.